BD82HM55-SLGZS Datasheet, PDF (33/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-11
8-12
8-13
8-10
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
8-26
8-27
8-28
8-29
8-30
8-31
S3/M3 to S0 Timing Diagram............................................................................... 364
S5/Moff - S5/M3 Timing Diagram ......................................................................... 364
S0 to S5 Timing Diagram .................................................................................... 365
DRAMPWRGD Timing Diagram ............................................................................. 365
Clock Cycle Time ............................................................................................... 366
Transmitting Position (Data to Strobe).................................................................. 366
Clock Timing ..................................................................................................... 366
Setup and Hold Times ........................................................................................ 367
Float Delay ....................................................................................................... 367
Pulse Width....................................................................................................... 367
Valid Delay from Rising Clock Edge ...................................................................... 367
Output Enable Delay .......................................................................................... 368
USB Rise and Fall Times ..................................................................................... 368
USB Jitter ......................................................................................................... 368
USB EOP Width ................................................................................................. 369
SMBus/SMLINK Transaction ................................................................................ 369
SMBus/SMLINK Timeout ..................................................................................... 369
SInPtIelT_®imHinigghs
......................................................................................................
Definition Audio Input and Output Timings ...........................................
370
370
Dual Channel Interface Timings ........................................................................... 371
Dual Channel Interface Timings ........................................................................... 371
LVDS Load and Transition Times .......................................................................... 371
Transmitting Position (Data to Strobe).................................................................. 372
PCI Express Transmitter Eye ............................................................................... 372
PCI Express Receiver Eye.................................................................................... 373
Measurement Points for Differential Waveforms. .................................................... 374
PCH Test Load ................................................................................................... 375
Controller Link Receive Timings ........................................................................... 375
Controller Link Receive Slew Rate ........................................................................ 375
Tables
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
3-1
Industry Specifications ......................................................................................... 44
IIIPnnnCtttIeeelllD^{®®®ev553i4cSS0eee0srriiaSeenssedrCCieFhhsuiippnCsscheetittipoDMsneesotsb.kS.i.ltee.o.r.pSv..eKS.r.UK.S.sU.K..s..U.....s..........................................................................................................................................................................................................................................................................}
48
55
56
57
Direct Media Interface Signals ............................................................................... 61
PCI Express* Signals............................................................................................ 61
Firmware Hub Interface Signals ............................................................................. 62
PCI Interface Signals............................................................................................ 63
Serial ATA Interface Signals .................................................................................. 65
LPC Interface Signals ........................................................................................... 68
Interrupt Signals ................................................................................................. 68
USB Interface Signals........................................................................................... 69
Power Management Interface Signals ..................................................................... 71
Processor Interface Signals ................................................................................... 74
SM Bus Interface Signals ...................................................................................... 74
System Management Interface Signals ................................................................... 75
Real Time Clock Interface ..................................................................................... 75
MInitsecle_®llaHnigehouDseSfiingintiaolns
...........................................................................................
Audio Link Signals.................................................................
76
77
Controller Link Signals.......................................................................................... 78
SInetreial_®l
Peripheral Interface (SPI)
Quiet System Technology
Signals..................................................................
Signals .................................................................
78
79
JTAG Signals ....................................................................................................... 80
Clock Interface Signals ......................................................................................... 80
LVDS Interface Signals ......................................................................................... 82
AInntaello_®gFDleisxpiblaley
Interface Signals
Display Interface
............................................................................
Signals .................................................................
83
84
Digital Display Interface Signals............................................................................. 84
General Purpose I/O Signals.................................................................................. 87
Manageability Signals ........................................................................................... 90
Power and Ground Signals .................................................................................... 91
Functional Strap Definitions................................................................................... 93
Integrated Pull-Up and Pull-Down Resistors ............................................................. 99
Datasheet
33