BD82HM55-SLGZS Datasheet, PDF (72/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Signal Description
Table 2-9.
Power Management Interface Signals (Sheet 2 of 3)
Name
Type
Description
MEPWROK
I
Management Engine Power OK: When asserted, this signal
indicates that power to the ME subsystem is stable.
PWRBTN#
Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is pressed
I for more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Override will occur even if the
system is in the S1–S4 states. This signal has an internal pull-up
resistor and has an internal 16 ms de-bounce on the input.
RI#
I
Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.
SYS_RESET#
System Reset: This pin forces an internal reset after being
I
debounced. The PCH will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before
forcing a reset on the system.
RSMRST#
Resume Well Reset: This signal is used for resetting the resume
I
power plane logic. This signal must be asserted for at least 10 ms after
the suspend power wells are valid. When de-asserted, this signal is an
indication that the suspend power wells are stable.
LAN_RST#
LAN Reset: When asserted, the internal LAN controller is in reset.
This signal must remain asserted until at least 1 ms after the LAN
power well (VccLAN) and ME power well (VccME3_3) are valid. Also,
LAN_RST# must assert a minimum of 40 ns before the LAN power rails
become inactive. When de-asserted, this signal is an indication that
I
LAN power wells are stable.
NOTES:
1.
If Intel LAN is enabled, LAN_RST# must be connected to the
same source as MEPWROK.
2.
If Intel LAN is not used or disabled, LAN_RST# must be
grounded through an external pull-down resistor.
LAN_PHY_PW
LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected
to LAN_DISABLE_N on the Intel 82567 GbE PHY. The PCH will drive
LAN_PHY_PWR_CTRL low to put the PHY into a low power state when
functionality is not needed.
R_CTRL /
GPIO12
O
NOTES:
LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is de-
asserted.
This signal can instead be used as GPIO12.
WAKE#
I
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.
SUS_STAT# /
GPIO61
Suspend Status: This signal is asserted by the PCH to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
O ^{refresh to suspend refresh mode. It can also be used by other}
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes.
This signal can instead be used as GPIO61.
SUSCLK /
GPIO62
Suspend Clock: This clock is an output of the RTC generator circuit to
O ^{use by other chips for refresh clock.}
This signal can instead be used as GPIO62.
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