English
Language : 

BD82HM55-SLGZS Datasheet, PDF (134/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset
Functional Description
5.3.1
5.3.1.1
5.3.1.2
5.3.1.2.1
5.3.1.2.2
5.3.1.3
GbE PCI Express* Bus Interface
The GbE controller has a PCI Express interface to the host processor and host memory.
The following sections detail the bus transactions.
Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer
connects to the device core using an implementation specific protocol. Through this
core-to-transaction-layer protocol, the application-specific parts of the device interact
with the subsystem and transmit and receive requests to or from the remote agent,
respectively.
Data Alignment
4 KB Boundary
PCI requests must never specify an address/length combination that causes a memory
space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests
into 4 KB-aligned requests (if needed). This does not pose any requirement on
software. However, if software allocates a buffer across a 4 KB boundary, hardware
issues multiple requests for the buffer. Software should consider aligning buffers to a
4 KB boundary in cases where it improves performance.
The alignment to the 4 KB boundaries is done in the core. The transaction layer does
not do any alignment according to these boundaries.
64 Bytes
PCI requests are multiples of 64 bytes and aligned to make better use of memory
controller resources. Writes, however, can be on any boundary and can cross a 64-byte
alignment boundary.
Configuration Request Retry Status
The integrated GbE controller might have a delay in initialization due to an NVM read. If
the NVM configuration read operation is not completed and the device receives a
configuration request, the device responds with a configuration request retry
completion status to terminate the request, and thus effectively stalls the configuration
request until such time that the sub-system has completed local initialization and is
ready to communicate with the host.
134
Datasheet