TDA5235 Datasheet, PDF (86/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Functional Description
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.
2.5.4 Interrupt Generation Unit
The TDA5235 is able to signal interrupts (NINT signal) to the external Application
Controller on one of the PPx port pins (for further details see Chapter 2.5.3 Digital
Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the
NINT signal based on the configuration of the Interrupt Mask register IM0. The Interrupt
Status register IS0 is set from the Interrupt Generation Unit, depending on which
interrupt occurred. The polarity of the interrupt can be changed in the PPCFG2 register.
Please note that during power up and brownout reset, the polarity of NINT signal is
always as described in Chapter 2.4.9.2 Chip Reset.
A Reset event has the highest priority. It sets all bits in the Status register to “1” and sets
the interrupt signal to “0”. The first interrupt after the Reset event will clear the Status
register and will set the interrupt signal to “1”, even if this interrupt is masked.
A Wake-up interrupt clears the FsyncA, FsyncB and the complementary Wake-up flag.
An Fsync interrupt clears the EOMA, EOMB, MIDA, MIDB and the complementary Fsync
flag.
The Interrupt Status register is always cleared after read out via SPI.
It is not possible to disable the Power On Reset Indicator Interrupt using the Interrupt
Mask register.
Some interrupts are not usable depending on the selected receive mode, which is
described in Chapter 2.5.1.2 Data Interface.
Interrupts for WU can be used in all receive modes.
Interrupts for FSync, MID and EOM can only be used in the receive modes POTP and
POF.
Data Sheet
86
V1.0, 2010-02-19