TDA5235 Datasheet, PDF (215/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description
A_CDRTOLC
CDR DC Chip Tolerance Register



8186('

Offset
049_H

72/&+,3+
Z
Reset Value
0C_H


72/&+,3/
Z
Field
Bits
UNUSED
7:6
TOLCHIPH 5:3
Type
-
w
TOLCHIPL 2:0
w
CDR DC Bit Tolerance Register
Description
UNUSED
Reset: 0_H
Duty Cycle Tolerance for Chip Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the following chip border.
Reset: 1_H
Duty Cycle Tolerance for Chip Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the previous chip border.
Reset: 4_H
A_CDRTOLB
CDR DC Bit Tolerance Register



8186('

Offset
04A_H

72/%,7+
Z
Reset Value
1E_H


72/%,7/
Z
Field
Bits
UNUSED
7:6
TOLBITH
5:3
TOLBITL
2:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Duty Cycle Tolerance for Bit Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the following bit border.
Reset: 3_H
Duty Cycle Tolerance for Bit Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the previous bit border.
Reset: 6_H
Data Sheet
215
V1.0, 2010-02-19