TDA5235 Datasheet, PDF (217/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TSI Detection Mode Register
TDA5235
Appendix
Register Description
A_TSIMODE
TSI Detection Mode Register


76,*56<
1
Z
76,:&$
Z
Offset
04D_H


&3+5$
Z
Reset Value
80_H


76,'(702'
Z
Field
Bits
TSIGRSYN 7
TSIWCA
6:3
CPHRA
2
TSIDETMOD 1:0
TSI Length Register A
Type
w
w
w
w
Description
TSI Gap Resync Mode (only for TSIDETMODE=2_H)
0_B Disabled - In this mode the GAPVAL and TSIGAP values are used,
so the overall GAP time can be
defined in T/16 steps.
1_B Enabled - PLL resync after TSI Gap
In this mode the T/2 GAP resolution can be set in the 5 MSB
TSIGAP register bits.
GAPVAL value is not used. Prefered in TSI Gap Mode.
Reset: 1_H
Wild Cards for 4 LSB chips of Correlator A
If all 4 chips are 0, the whole TSI pattern for Correlator A is valid
if a chip is 1, the corresponding chip from the TSI pattern is ignored
Reset: 0_H
Code Phase Readjustment in Payload
0_B disabled - code polarity is defined by the TSI pattern
1_B enabled - code phase readjustment in payload
Reset: 0_H
TSI Detection Mode
00_B 16 Bit TSI Mode - TSI configuration B AND A valid (sequentially),
B is valid if A_TSILENA=16 (=10_H) and the A_TSILENB > 0
01_B 8 Bit Parallel TSI Mode - TSI configurations A OR B (parallel)
10_B 8 Bit TSI Gap Mode - TSI configurations A AND B with Gap
(sequentially with Gap between TSIA & TSIB)
11_B 8 Bit Extended TSI Mode - TSI configurations A OR B (parallel with
matching information), dependent on found TSI A or B, 0 resp. 1 will
be sent as 1st received bit.
Reset: 0_H
A_TSILENA
TSI Length Register A
Data Sheet
Offset
04E_H
217
Reset Value
00_H
V1.0, 2010-02-19