TDA5235 Datasheet, PDF (204/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

RSSI Peak Detector Bit Position Register
TDA5235
Appendix
Register Description
A_PKBITPOS
RSSI Peak Detector Bit Position Register

Offset
037_H
566,'/<
Z
Reset Value
00_H

Field
Bits
RSSIDLY
7:0
Type
w
Description
RSSI Detector Start-up Delay for RSSIPPL register
Min: 00h: 0 bit delay (Start with first bit after FSYNC)
Max: FFh: 255 bit delay
Note: Due to filtering and signal computation, the latency T1 and T2 have
to be added
Reset: 00_H
Image Supression Fc Selection Register
A_ISUPFCSEL
Image Supression Fc Selection Register
Offset
038_H



8186('
5HV

Reset Value
07_H


)&6(/
Z
Field
Bits
UNUSED
7:4
FCSEL
2:0
Data Sheet
Type
-
w
Description
UNUSED
Reset: 0_H
Image Supression Filter Corner Frequency Selection for FSK signal
path
000_B 33 kHz
001_B 46 kHz
010_B 65 kHz
011_B 93 kHz
100_B 132 kHz
101_B 190 kHz
110_B 239 kHz
111_B 282 kHz
Reset: 7_H
204
V1.0, 2010-02-19