TDA5235 Datasheet, PDF (219/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description
A_TSIGAP
TSI Gap Length Register

76,*$3
Z
Offset
050_H

Reset Value
00_H


*$39$/
Z
Field
Bits
TSIGAP
7:3
GAPVAL
2:0
Type
w
w
Description
TSI Gap (T/2 bit resolution)
1Fh: 15 1/2 bit gap
00h: 0 bit gap
TSIGAP is used to lock the PLL after TSI A is found, if the TSI detection
mode 10b is selected.
Reset: 00_H
TSI Gap (T/16 bit resolution)
111b: 7/16 bit gap
000b: 0 bit gap
GAPVAL is used to correct the DCO phase after TSIGAP time, if
A_TSIMODE.TSIGRSYN is disabled
Reset: 0_H
TSI Pattern Data Reference A Register 0
A_TSIPTA0
TSI Pattern Data Reference A Register 0

Offset
051_H
76,37$
Z
Reset Value
00_H

Field
Bits
TSIPTA0
7:0
Type
w
Description
Data Pattern for TSI comparison: Bit 7...Bit 0(LSB) (in Chips)
Reset: 00_H
TSI Pattern Data Reference A Register 1
A_TSIPTA1
TSI Pattern Data Reference A Register 1
Data Sheet
Offset
052_H
219
Reset Value
00_H
V1.0, 2010-02-19