TDA5235 Datasheet, PDF (214/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description
Field
ISAT
Bits
Type Description
1:0
w
I Value Saturation. The saturation of the I-Loop-Filter accumulator
will be set according to the
ISAT value. Remark that the internal phase resolution of the phase
detector is 1/16 bit.
00_B saturation to 1/16 bit
01_B saturation to 2/16 bit
10_B saturation to 4/16 bit
11_B saturation to 8/16 bit
Reset: 1_H
Clock and Data Recovery RUNIN Configuration Register
A_CDRRI
Clock and Data Recovery RUNIN
Configuration Register

8186('

Offset
048_H
Reset Value
01_H




'5/,0(1
581/(1
Z
Z
Field
Bits
UNUSED
7:3
DRLIMEN
2
Type
-
w
RUNLEN
1:0
w
CDR DC Chip Tolerance Register
Description
UNUSED
Reset: 00_H
Enable data rate error acceptance limitation.
The limits are defined in CDRDRTHRP and CDRDRTHRN registers.
0_B Disabled
1_B Enabled
Reset: 0_H
RUNIN Length. The RUNIN length is equal to PLL-start-value
calculation time. This means
that the shorter RUNIN length decreases the data rate offset calculation
accuracy and symbol synchronization found signal generation stability.
Note that the RUNLEN have to be changed together with the TSI
configuration registers.
00_B 8 chips
01_B 7 chips
10_B 6 chips
11_B 5 chips
Reset: 1_H
Data Sheet
214
V1.0, 2010-02-19