TDA5235 Datasheet, PDF (212/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description


3'65
Z

3+'(1
Z

3+'(1
Z


39$/
Z


36$7
Z
Field
Bits
PDSR
7:6
PHDEN1
5
PHDEN0
4
PVAL
3:2
PSAT
1:0
Type
w
w
w
w
w
Description
Peak-Detector slew rate. The slew rate of the Peak-Detector in the
clock-recovery path will be set with
PDSR. Actually, Peak-Detector part of Signal Detector Block
00_B up/down = 1/64
01_B up = 1/64; down = 1/128
10_B up = 1/32; down = 1/128
11_B up = 1/32; down = 1/256
Reset: 3_H
Phase detector error (PDE) outer tolerance range
0_B Disabled: PDEout = PDEin.
1_B Enabled: If PDEin > abs(7/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 1_H
Phase detector error (PDE) inner tolerance range
0_B Disabled: PDEout = PDEin.
1_B Enabled: If PDEin < abs(1/16) bit then PDEout = 0 else PDEout =
PDEin.
Reset: 0_H
P Value. The PVAL is the P value of the Clock-Recovery PI Loop-
Filter. The Phase-
Detector output error will be multiplied with the set value.
00_B 1/1 phase detector error
01_B 1/2 phase detector error
10_B 1/4 phase detector error
11_B 1/8 phase detector error
Reset: 1_H
P Value Saturation. The saturation of the P-Loop-Filter path will be
set according to the PSAT
value. Remark that the internal phase resolution of the phase detector is
1/16 bit.
00_B saturation to 1/16 bit
01_B saturation to 2/16 bit
10_B saturation to 4/16 bit
11_B saturation to 8/16 bit
Reset: 2_H
Clock and Data Recovery Configuration Register
Data Sheet
212
V1.0, 2010-02-19