TDA5235 Datasheet, PDF (203/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description
A_DIGRXC
Digital Receiver Configuration Register
Offset
036_H
Reset Value
40_H

,1,7'5;
(6
Z

,1,7)5&
6
Z


&2'(
Z

&+,3',1
9
Z

',19(;7
Z

$$)%<3
Z

$$))&6(
/
Z
Field
Bits
INITDRXES 7
INITFRCS
6
CODE
5:4
CHIPDINV 3
DINVEXT
2
AAFBYP
1
AAFFCSEL 0
Type
w
w
w
w
w
w
w
Description
Init the Digital Receiver at EOM or Loss of Symbol Sync (e.g. for
initialization of the Peak Memory Filter)
0_B Disabled
1_B Enabled
Reset: 0_H
Init the Framer at Cycle Start in RMSP.
If disabled, the WUP Data can be used as part of TSI as well in case the
modulation type is the same for SPM and RMSP
0_B Disabled
1_B Enabled
Reset: 1_H
Encoding Mode Selection
00_B Manchester Code
01_B Differential Manchester Code
10_B Biphase Space
11_B Biphase Mark
Reset: 0_H
Baseband Chip Data Inversion for CH_DATA and Decoder/Framer
input. Therefore Inverted Manchester and Inverted Differential
Manchester can be decoded internally.
0_B Not inverted
1_B Inverted
Reset: 0_H
Data Inversion of signal DATA and DATA_MATCHFIL for External
Processing
0_B Not inverted
1_B Inverted
Reset: 0_H
Anti-Alliasing Filter Bypass for RSSI pin
0_B Not bypassed
1_B Bypassed
Reset: 0_H
Anti-Alliasing Filter Corner Frequency Select
0_B 40 kHz
1_B 80 kHz
Reset: 0_H
Data Sheet
203
V1.0, 2010-02-19