TDA5235 Datasheet, PDF(173/259 Page) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

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TDA5235 Datasheet, PDF (173/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

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TDA5235

Appendix

Register Overview

Table 2 Register Overview and Reset Value (contâd)

Register Short Name Register Long Name

Offset Address

A_MID16

A_MID17

A_MID18

A_MID19

A_MIDC0

A_MIDC1

A_IF1

A_WUC

A_WUPAT0

A_WUPAT1

A_WUBCNT

A_WURSSITH1

A_WURSSIBL1

Message ID Register 16

Message ID Register 17

Message ID Register 18

Message ID Register 19

Message ID Control Register 0

Message ID Control Register 1

IF1 Register

Wake-Up Control Register

Wake-Up Pattern Register 0

Wake-Up Pattern Register 1

Wake-Up Bit or Chip Count Register

RSSI Wake-Up Threshold for Channel 1 Register

RSSI Wake-Up Blocking Level Low Channel 1

Register

010H

011H

012H

013H

014H

015H

016H

017H

018H

019H

01AH

01BH

01CH

A_WURSSIBH1

RSSI Wake-Up Blocking Level High Channel 1

Register

01DH

A_SIGDETSAT

A_WULOT

A_SYSRCTO

A_TOTIM_SYNC

A_TOTIM_TSI

A_TOTIM_EOM

A_AFCLIMIT

A_AFCAGCD

A_AFCSFCFG

A_AFCK1CFG0

A_AFCK1CFG1

A_AFCK2CFG0

A_AFCK2CFG1

A_PMFUDSF

A_AGCSFCFG

A_AGCCFG0

A_AGCCFG1

A_AGCTHR

A_DIGRXC

A_PKBITPOS

A_ISUPFCSEL

A_PDECF

A_PDECSCFSK

Signal Detector Saturation Threshold Register

Wake-up on Level Observation Time Register

Synchronization Search Time-Out Register

SYNC Timeout Timer Register

TSI Timeout Timer Register

EOM Timeout Timer Register

AFC Limit Configuration Register

AFC/AGC Freeze Delay Register

AFC Start/Freeze Configuration Register

AFC Integrator 1 Gain Register 0

AFC Integrator 1 Gain Register 1

AFC Integrator 2 Gain Register 0

AFC Integrator 2 Gain Register 1

Peak Memory Filter Up-Down Factor Register

AGC Start/Freeze Configuration Register

AGC Configuration Register 0

AGC Configuration Register 1

AGC Threshold Register

Digital Receiver Configuration Register

RSSI Peak Detector Bit Position Register

Image Supression Fc Selection Register

Pre Decimation Factor Register

Pre Decimation Scaling Register FSK Mode

024H

025H

026H

027H

028H

029H

02AH

02BH

02CH

02DH

02EH

02FH

030H

031H

032H

033H

034H

035H

036H

037H

038H

039H

03AH

Reset Value

00H

00H

00H

00H

00H

00H

20H

04H

00H

00H

00H

00H

FFH

00H

10H

00H

87H

FFH

00H

00H

02H

00H

00H

00H

00H

00H

00H

42H

00H

2BH

03H

08H

40H

00H

07H

00H

00H

Data Sheet

173

V1.0, 2010-02-19

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