TDA5235 Datasheet, PDF (248/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description
Field
Bits
RSSIPWU
7:0
Type
-
Interrupt Status Register 0
Description
Peak Detector Level at Wakeup
Set at every WU event and also set at the end of every
configuration/channel cycle within a Self Polling period.
Cleared at Reset only.
Reset: 00_H
IS0
Interrupt Status Register 0

(20%
UF

0,')%
UF

)6<1&%
UF
Offset
0A8_H

:8%
UF

(20$
UF

0,')$
UF
Reset Value
FF_H

)6<1&$
UF

:8$
UF
Field
Bits
EOMB
7
MIDFB
6
FSYNCB
5
WUB
4
EOMA
3
Type
rc
rc
rc
rc
rc
Description
Interrupt Request by "End of Message" from Configuration B (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Message ID Found" from Configuration B
(Reset event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Frame Sync" from Configuration B (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "Wake Up" from Configuration B (Reset event
sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Interrupt Request by "End of Message" from Configuration A (Reset
event sets all Bits to 1)
0_B Not detected
1_B Detected
Reset: 1_H
Data Sheet
248
V1.0, 2010-02-19