TDA5235 Datasheet, PDF (192/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Appendix
Register Description


:8566,%/
Z
Field
Bits
WURSSIBL1 7:0
Type
w
Description
Wake Up on RSSI Blocking Level LOW for Channel 1
Reset: FF_H
RSSI Wake-Up Blocking Level High Channel 1 Register
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel
1 Register
Offset
01D_H

:8566,%+
Z
Reset Value
00_H

Field
Bits
WURSSIBH1 7:0
Type
w
Description
Wake Up on RSSI Blocking Level HIGH for Channel 1, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00_H
Signal Detector Saturation Threshold Register
A_SIGDETSAT
Signal Detector Saturation Threshold
Register

Offset
024_H
6,*'(76$7
Z
Reset Value
10_H

Data Sheet
192
V1.0, 2010-02-19