TDA5235 Datasheet, PDF (82/259 Pages) Infineon Technologies AG – Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing

TDA5235
Functional Description
2.5.2 Receive FIFO
The Receive FIFO is the storage of the received data frames and is only used in the POF
Mode. It is written during data reception. The host microcontroller is able to start reading
via SPI right after frame sync (interrupt) or in the most common case right after detection
of EOM (interrupt). The FIFO can store up to 256 received data bits. If the expected data
transmission contains more bits (note that in TSI 8-bit Extended Mode one bit is added
in front of the real payload to indicate which of the two TSI pattern has matched), reading
from FIFO must start a certain time after frame sync to prevent an overrun.
Architecture
The 256-bit receive FIFO is based on a bit-addressable 2-port memory architecture.
Data
from
Digital-
Receiver
Data Clock
from FSM
INITFIFO
FSINITFIFO
InitFIFO
Write Address
Pointer
(Up-Counter)
ENABLE
RESET
Write-Port
Bit-Address
In
1 of 16 Decoder
byte 0
byte 16
byte 1
byte 17
byte 2
byte 18
byte 3
byte 19
byte 4
byte 20
byte 5
byte 21
byte 6
byte 22
byte 7 256-bit byte 23
byMte 8emory-Arbryatey24
byte 9
byte 25
byte 10
byte 26
byte 11
byte 27
byte 12
byte 28
byte 13
byte 29
byte 14
byte 30
byte 15
byte 31
16 to 1 MUX
Out
Bit-Address
Read-Port
Read Address
Pointer
(Up-Counter)
RESET
ENABLE
SCLK
to
SPI-Bus
from
Digital-
Receiver
FSync
EOM
FIFOLK
FIFO-
Controller
FIFO-Overflow
# of Valid Bits
SDO-Frame
Generator
SDO
fifolk
to FSM
Figure 53 Receive FIFO
The write port is controlled by the Digital Receiver using the Write Address Pointer.
Writing data into the FIFO starts with the detection of a TSI. The Write Address Pointer
is incremented with each data clock signal generated by the Digital Receiver. The read
port is controlled by the SPI controller using the Read Address Pointer. Each bit read
from the SPI controller increments the Read Address Pointer. The Read and Write
Address Pointers jump from their maximum value (255_d) to address zero. Writing to the
FIFO stops at EOM or after Sync loss.
Data Sheet
82
V1.0, 2010-02-19