ICS1892 Datasheet, PDF (88/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892 Data Sheet
Chapter 8 Management Register Set
8.11.7 Invalid Error Code Test (bit 16.2)
The Invalid Error Code Test bit allows an STA to force the ICS1892 to transmit symbols that are typically
classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the
serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC
4B/5B definition.
When this bit is logic:
• Zero, the ISO/IEC defined 4B/5B translation takes place.
• One – and the TXER signal is asserted by the MAC/repeater – the MII input nibbles are translated
according to Table 8-17.
Table 8-17. Invalid Error Code Translation Table
Symbol Meaning
V
V
V
V
H
V
V
R
V
T
V
K
V
V (S)
J
I
Invalid Code
Invalid Code
Invalid Code
Invalid Code
Error
Invalid Code
Invalid Code
ESD
Invalid Code
ESD
Invalid Code
SSD
Invalid Code
Invalid Code
SSD
Idle
MII Input Translation
Nibble
0000
00000
0001
00001
0010
00010
0011
00011
0100
00100
0101
00101
0110
00110
0111
00111
1000
00000
1001
01101
1010
01100
1011
10001
1100
10000
1101
11001
1110
11000
1111
11111
8.11.8 ICS Reserved (bit 16.1)
See Section 8.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
8.11.9 Stream Cipher Disable (bit 16.0)
The Stream Cipher Disable bit allows an STA to control whether the ICS1892 employs the Stream Cipher
Scrambler in the transmit and receive data paths. When this bit is set to logic:
• Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.
• One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data
stream (for example, the ICS1892 transmits unscrambled IDLES, and so forth.
Note: The Stream Cipher Scrambler can be used only for 100-MHz operations.
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
88
February 26, 2001