ICS1892 Datasheet, PDF (140/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892 Data Sheet
Chapter 10 DC and AC Operating Conditions
10.5.17 Reset: Hardware Reset and Power-Down
Table 10-24 lists the significant time periods for the hardware reset and power-down reset (which consists
of timings of signals on the REF_IN, RESET*, and TXCLK pins). Figure 10-17 shows the timing diagram for
the time periods.
Table 10-24. Hardware Reset and Power-Down Timing
Time
Period
Parameter
t1 RESET* Active to Device Isolation and
Initialization
t2 Minimum RESET* Pulse Width
t3 RESET* Released to TXCLK Valid
Conditions Min. Typ. Max. Units
–
– 65 –
ns
–
200 –
–
ns
–
– 53 200 ms
Figure 10-17. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESET*
t1
t2
t3
TXCLK
Valid
Power
Consumption
(AC only)
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
140
February 26, 2001