ICS1892 Datasheet, PDF (135/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892
Chapter 10 DC and AC Operating Conditions
10.5.12 MII / 100M Stream Interface: Transmit Latency
Table 10-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
periods consist of timings of signals on the following pins: TXEN, TXCLK, TXD (that is, TXD[3:0]), and
TP_TX (that is, the TP_TXP and TP_TXN pins). Figure 10-12 shows the timing diagram for the time
periods.
Table 10-19. MII / 100M Stream Interface Transmit Latency
Time
Period
Parameter
Conditions
Min. Typ. Max. Units
t1 TXEN Sampled to MDI Output of First MII
Bit of /J/ †
– 4 4 Bit times
t2 TXD Sampled to MDI Output of First 100M Stream Interface – 4 4 Bit times
Bit
† The IEEE maximum is 18 bit times.
Figure 10-12. MII / 100M Stream Interface Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
Preamble /J/ Preamble /K/
TP_TX*
t1
t2
*Shown
unscrambled.
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
135
February 26, 2001