ICS1892 Datasheet, PDF (126/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892 Data Sheet
Chapter 10 DC and AC Operating Conditions
10.5.3 Timing for Receive Clock (RXCLK) Pin
Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pin for the various
interfaces. Figure 10-3 shows the timing diagram for the time periods.
Table 10-10. MII Receive Clock Timing
Time
Period
Parameter
Conditions
t1 RXCLK Duty Cycle
–
t2a RXCLK Period
100M MII (100Base-TX)
t2b RXCLK Period
10M MII (10Base-T)
t2c RXCLK Period
100M Symbol Interface (100Base-TX)
t2d RXCLK Period
10M Symbol Interface (10Base-T)
Min. Typ. Max. Units
35
50
65
%
–
40
–
ns
– 400 –
ns
–
40
–
ns
– 100 –
ns
Figure 10-3. Receive Clock Timing Diagram
t1
RXCLK
t2
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
126
February 26, 2001