ICS1892 Datasheet, PDF (138/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892 Data Sheet
Chapter 10 DC and AC Operating Conditions
10.5.15 Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-22 lists the significant time periods for the MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins: CRS, COL, and TP_RX (that is, the TP_RXP and
TP_RXN pins). Figure 10-15 shows the timing diagram for the time periods.
Table 10-22. MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
t1 First Bit of /J/ into TP_RX to CRS
Assert †
t2 First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
Conditions
Min. Typ. Max. Units
–
9
–
13 Bit times
Half-Duplex Mode 9
–
13 Bit times
t3 First Bit of /T/ into TP_RX to CRS
De-Assert ‡
–
13
–
17 Bit times
t4 First Bit of /T/ Received into TP_RX to Half-Duplex Mode –
COL De-Assert ‡
–
14 Bit times
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-15. MDI Input to Carrier Assertion / De-Assertion Timing Diagram
TP_RX*
CRS
First bit
t1
First bit of /T/
t3
COL
t2
t4
*Shown
unscrambled.
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
138
February 26, 2001