ICS1892 Datasheet, PDF (17/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892
Chapter 5 Operating Modes Overview
Chapter 5 Operating Modes Overview
The ICS1892 operating modes and interfaces are configurable with one of two methods. The first
configuration method is by using hardware pins. With this method, the HW/SW (hardware/software) pin
determines whether it is the hardware pins or the register bits that have priority for configuring the ICS1892.
The second – and more typical – configuration method is by using register bits, typically controlled from
software. The register bits are accessible through a standard MII (Media Independent Interface) Serial
Management Port. Even when the MAC/Repeater Interface is not supporting the standard MII Data
Interface, access to the Serial Management Port is provided (that is, operation of the Serial Management
Port is independent of the MAC/Repeater Interface configuration).
The ICS1892 provides a number of configuration functions to support a variety of operations. For example,
the MAC/Repeater Interface can be configured to operate as a 10M MII, a 100M MII, a 100M Symbol
Interface, a 10M Serial Interface, or a Link Pulse Interface. The protocol on the Medium Dependent
Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or
full-duplex modes.
The ICS1892 is fully compliant with the ISO/IEC 8802-3 standard, as it pertains to both 10Base-T and
100Base-TX operations. The feature-rich ICS1892 allows easy migration from 10-Mbps to 100-Mbps
operations as well as from systems that require support of both 10M and 100M links.
This chapter is an overview of the following ICS1892 modes of operation:
• Section 5.1, “Reset Operations”
• Section 5.2, “Power-Down Operations”
• Section 5.3, “Automatic Power-Saving Operations”
• Section 5.4, “Auto-Negotiation Operations”
• Section 5.5, “100Base-TX Operations”
• Section 5.6, “10Base-T Operations”
• Section 5.7, “Half-Duplex and Full-Duplex Operations”
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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February 26, 2001