ICS1892 Datasheet, PDF (42/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892 Data Sheet
Chapter 7 Functional Blocks
7.3.3 PCS/PMA Transmit Modules
Both the PCS and PMA sublayers have Transmit modules.
7.3.3.1 PCS Transmit Module
The ICS1892 PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts the
nibbles into 5-bit ‘code groups’ (referred to here as ‘symbols’). Then the PCS Transmit module performs a
parallel-to-serial conversion on the symbols, and subsequently passes the resulting serial bit stream to the
PMA sublayer.
The first 16 nibbles of each MAC/Repeater Frame represent the Frame Preamble. The PCS replaces the
first two nibbles of the Frame Preamble with the Start-of-Stream Delimiter (SSD), that is, the symbols /J/K/.
After receipt of the last Frame nibble, detected when TX_EN = FALSE, the PCS appends to the end of the
Frame an End-of-Stream Delimiter (ESD), that is, the symbols /T/R/. (The ICS1892 PCS does not alter any
other data included within the Frame.)
The PCS Transmit module also performs collision detection. When the transmission and reception of data
occur simultaneously, then in compliance with the ISO/IEC specification, when the ICS1892 is in:
• Half-duplex mode, the ICS1892 asserts the collision detection signal (COL).
• Full-duplex mode, COL is always FALSE.
7.3.3.2 PMA Transmit Module
The ICS1892 PMA Transmit module accepts a serial bit stream from the PCS and converts it into NRZI
format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium
Dependent (TP-PMD) sublayer.
The ICS1892 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock
Reference Interface. When the ICS1892 is configured for an interface that is:
• 10M MII (that is, 10Base-T), the TXCLK signal is 2.5 MHz
• 10M Serial Interface, the TXCLK signal is 10 MHz
• Either of the following, the TXCLK signal (a buffered version of the REF_IN signal) is 25 MHz:
– 100M MII (that is, 100Base-TX)
– 100M Symbol Interface
Note:
1. All of the TXCLK signals are derived from the REF_IN signal that goes to the digital PLL.
2. For the MII, for both the 10Base-T and 100Base-TX modes, the clock that is generated synchronizes
all data transfers across the MII.
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
42
February 26, 2001