ICS1892 Datasheet, PDF (137/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892
Chapter 10 DC and AC Operating Conditions
10.5.14 100M MII / 100M Stream Interface: Receive Latency
Table 10-21 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The
time periods consist of timings of signals on the following pins: TP_RX (that is, TP_RXP and TP_RXN),
RXCLK, and RXD (that is, RXD[3:0]). Figure 10-14 shows the timing diagram for the time periods.
Table 10-21. 100M MII / 100M Stream Interface Receive Latency Timing
Time
Period
Parameter
Conditions
Min. Typ. Max. Units
t1 First Bit of /J/ into TP_RX to /J/ on RXD 100M MII
– 16.9 17 Bit times
t2 First Bit of /J/ into TP_RX to /J/ on RXD 100M Stream Interface – TBD 12.5 Bit times
Figure 10-14. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram
TP_RX*
RXCLK
RXD
t1
t2
*Shown
unscrambled.
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
137
February 26, 2001