ICS1892 Datasheet, PDF (136/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892 Data Sheet
Chapter 10 DC and AC Operating Conditions
10.5.13 MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 10-20 lists the significant time periods for the MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins: TXEN, TXCLK, and CRS.
Figure 10-13 shows the timing diagram for the time periods.
Table 10-20. MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
Conditions Min. Typ. Max. Units
t1 TXEN Sampled Asserted to CRS Assert
–
– < 1 1 Bit times
t2 TXEN Sampled De-Asserted to CRS De-Asserted
–
– <1 1
t3 TXEN De-Asserted to CRS De-Asserted
–
––4
Figure 10-13. MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
t3
TXEN
TXCLK
CRS
t2
t1
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
136
February 26, 2001