ICS1892 Datasheet, PDF (7/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892
Table of Contents
Table of Contents
Section
8.14
8.14.1
8.14.2
8.14.3
8.14.4
8.14.5
8.14.6
Chapter 9
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
Chapter 10
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10
10.5.11
10.5.12
10.5.13
Title
Page
Register 19: Extended Control Register 2 ................................................. 98
Node/Repeater Configuration (bit 19.15) ................................................... 99
Hardware/Software Priority Status (bit 19.14) ........................................... 99
Remote Fault (bit 19.13) ............................................................................ 99
ICS Reserved (bits 19.12:2) ...................................................................... 99
Automatic 10Base-T Power-Down (bit 19.1) ........................................... 100
Automatic 100Base-TX Power-Down (bit 19.0) ....................................... 100
ICS 1892 Pin Listing and Pin Descriptions ..................................... 101
ICS 1892 Pin Listings .............................................................................. 101
Pin Listing by Pin Number ....................................................................... 102
Pin Listings by Alphabetical Pin Name .................................................... 103
ICS 1892 Pin Descriptions ....................................................................... 104
Transformer Interface Pins ...................................................................... 104
Multifunction (Multiplexed) Pins: PHY Address and LED Pins ................ 105
Configuration Pins ................................................................................... 106
MAC/Repeater Interface Pins .................................................................. 109
Reserved Pins ......................................................................................... 118
Ground and Power Pins .......................................................................... 118
DC and AC Operating Conditions .................................................. 120
Absolute Maximum Ratings ..................................................................... 120
Recommended Operating Conditions ..................................................... 120
Recommended Component Values ......................................................... 121
DC Operating Characteristics .................................................................. 122
DC Operating Characteristics for Supply Current .................................... 122
DC Operating Characteristics for TTL Inputs and Outputs ...................... 122
DC Operating Characteristics for REF_IN ............................................... 122
DC Operating Characteristics for Media Independent Interface .............. 123
Timing Diagrams ..................................................................................... 124
Timing for Clock Reference In (REF_IN) Pin ........................................... 124
Timing for Transmit Clock (TXCLK) Pin .................................................. 125
Timing for Receive Clock (RXCLK) Pin ................................................... 126
100M MII / 100M Stream Interface: Synchronous Transmit Timing ........ 127
10M MII: Synchronous Transmit Timing .................................................. 128
MII / 100M Stream Interface: Synchronous Receive Timing ................... 129
MII Management Interface Timing ........................................................... 130
10M Serial Interface: Receive Latency .................................................... 131
10M Media Independent Interface: Receive Latency .............................. 132
10M Serial Interface: Transmit Latency ................................................... 133
10M Media Independent Interface: Transmit Latency ............................. 134
MII / 100M Stream Interface: Transmit Latency ...................................... 135
MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) ............ 136
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7
February 26, 2001