ICS1892 Datasheet, PDF (139/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892
Chapter 10 DC and AC Operating Conditions
10.5.16 Reset: Power-On Reset
Table 10-23 lists the significant time periods for the power-on reset (which consists of timings of signals on
the V_DD and TXCLK pins). Figure 10-16 shows the timing diagram for the time periods.
Table 10-23. Power-On Reset Timing
Time
Period
Parameter
t1 V_DD ≥ 4.75 V to Reset Complete
Conditions Min. Typ. Max. Units
–
109 – 200 ms
Figure 10-16. Power-On Reset Timing Diagram
4.75 V
V_DD
t1
TXCLK
Valid
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
139
February 26, 2001