ICS1892 Datasheet, PDF (125/148 Pages) Integrated Circuit Systems – 10Base-T/100Base-TX Integrated PHYceiver

ICS1892
Chapter 10 DC and AC Operating Conditions
10.5.2 Timing for Transmit Clock (TXCLK) Pin
Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pin for the various
interfaces. Figure 10-2 shows the timing diagram for the time periods.
Table 10-9. Transmit Clock Timing
Time
Period
Parameter
Conditions
t1 TXCLK Duty Cycle
–
t2a TXCLK Period
100M MII (100Base-TX)
t2b TXCLK Period
10M MII (10Base-T)
t2c TXCLK Period
100M Symbol Interface (100Base-TX)
t2d TXCLK Period
10M Symbol Interface (10Base-T)
Min. Typ. Max. Units
35
50
65
%
–
40
–
ns
– 400 –
ns
–
40
–
ns
– 100 –
ns
Figure 10-2. Transmit Clock Timing Diagram
t1
TXCLK
t2x
ICS1892, Rev. D, 2/26/01
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
125
February 26, 2001