HN29W25611T Datasheet, PDF (9/42 Pages) Hitachi Semiconductor – 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit)

HN29W25611T-50H
Fifth bus cycle
Sixth bus cycle
Command
Bus Operation Data in
cycles mode
Operation Data in
mode
Read
Serial read (1) (Without CA) 3
(With CA) 3 + 2h*⁶ Write
CA (2)*⁵
Serial read (2)
3
Read identifier codes
1
Data recovery read
1
Auto erase Single sector
4
Auto program Program (1) (Without
4
CA*⁷)
(With CA*⁷) 4 + 2h*⁶ Write
CA (2)*⁵
Write
40H^{*11, 12}
Program (2)*¹⁰
4
Program (3) (Control bytes)*⁷ 4
Program (4) (WithoutCA*⁷) 4
(With CA*⁷) 4 + 2h*⁶ Write
CA (2)
Write
40H^{*11, 12}
Reset
1
Clear status register
1
Data recovery write
4
Notes: 1. Commands and sector address are latched at rising edge of WE pulses. Program data is latched
at rising edge of SC pulses.
2. The chip is in the read status register mode when RES is set to V_IHR first time after the power up.
3. Refer to the command read and write mode in mode selection.
4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A13).
5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11).
(0 ≤ A11 to A0 ≤ 83FH)
6. The variable h is the input number of times of set of CA (1) and CA (2) (1 ≤ h ≤ 2048 + 64).
Set of CA (1) and CA (2) can be input not only one time but free times.
7. By using program (1) and (3), data can additionally be programmed for each sector before erase.
8. ID = Identifier code; Manufacturer code (07H), Device code (99H).
9. The manufacturer identifier code is output when CDE is low and the device identifier code is output
when CDE is high.
10. Before program (2) operations, data in the programmed sector must be erased.
11. No commands can be written during auto program and erase (when the RDY/Busy pin outputs a
V_OL).
12. The fourth or sixth cycle of the auto program comes after the program data input is complete.
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