MCF5272CVM66 Datasheet, PDF (97/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

ColdFire Core
Table 2-21. MCF5272 Exceptions (continued)
Exception
Description
Illegal
Instruction
On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC) are decoded and
generate an illegal instruction exception. Additionally, attempting to execute an illegal line A or line F opcode
generates unique exception types: vectors 10 and 11, respectively. If any other nonsupported opcode is
executed, the resulting operation is undefined.
ColdFire processors do not provide illegal instruction detection on extension words of any instruction, including
MOVEC. Attempting to execute an instruction with an illegal extension word causes undefined results.
Divide by Zero Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points to the
faulting instruction (DIVU, DIVS, REMU, REMS).
Privilege
Violation
Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire
Programmer’s Reference Manual lists supervisor- and user-mode instructions.
Trace
Exception
ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode
(SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program
execution.
The only exception to this definition is the STOP instruction. If the processor is in trace mode, the instruction
before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points
to the STOP opcode. When the trace handler is exited, the STOP instruction is executed, loading the SR with
the immediate operand from the instruction. The processor then generates a trace exception. The PC in the
exception stack frame points to the instruction after STOP, and the SR reflects the just-loaded value.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets the
trace bit in the SR, hardware loads the SR and generates a trace exception. The PC in the exception stack
frame points to the instruction after STOP, and the SR reflects the just-loaded value. Because ColdFire
processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating
system to check for trace mode after processing other exception types. As an example, consider a TRAP
instruction executing in trace mode. The processor initiates the TRAP exception and passes control to the
corresponding handler. If the system requires that a trace exception be processed, the TRAP exception
handler must check for this condition (SR[15] in the exception stack frame asserted) and pass control to the
trace handler before returning from the original exception.
Debug
Interrupt
Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the processor
internally calculates the vector number (12). Additionally, the M bit and the interrupt priority mask fields of the
SR are unaffected by the interrupt. See Section 2.2.2.1, “Status Register (SR).”
RTE and
Format Error
Exceptions
When an RTE instruction executes, the processor first examines the 4-bit format field to validate the frame type.
For a ColdFire processor, any attempted execution of an RTE where the format is not equal to {4,5,6,7}
generates a format error. The exception stack frame for the format error is created without disturbing the
original exception frame and the stacked PC points to RTE.The selection of the format value provides limited
debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the
top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero; so, attempting
an RTE using this old format generates a format error on a ColdFire processor.
If the format field defines a valid type, the processor does the following:
1 Reloads the SR operand.
2 Fetches the second longword operand.
3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first longword
fetch.
4 Transfers control to the instruction address defined by the second longword operand in the stack frame.
TRAP
Executing TRAP always forces an exception and is useful for implementing system calls. The trap instruction
may be used to change from user to supervisor mode.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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