MCF5272CVM66 Datasheet, PDF (157/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Debug Support
Table 5-22. PST/DDATA Specification for User-Mode Instructions (continued)
Instruction
Operand Syntax
PST/DDATA
rems.l
<ea>y,Dx:Dw PST = 0x1, {PST = 0xB, DD = source operand}
remu.l
<ea>y,Dx:Dw PST = 0x1, {PST = 0xB, DD = source operand}
rts
PST = 0x1, {PST = 0xB, DD = source operand},
PST = 0x5, {PST = [0x9AB], DD = target address}
scc
Dx
PST = 0x1
sub.l
<ea>y,Rx
PST = 0x1, {PST = 0xB, DD = source operand}
sub.l
Dy,<ea>x
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
subi.l
#imm,Dx
PST = 0x1
subq.l
#imm,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
subx.l
Dy,Dx
PST = 0x1
swap
trap
Dx
#imm
PST = 0x1
PST = 0x1³
trapf
PST = 0x1
tst.b
<ea>x
PST = 0x1, {PST = 0x8, DD = source operand}
tst.l
<ea>x
PST = 0x1, {PST = 0xB, DD = source operand}
tst.w
<ea>x
PST = 0x1, {PST = 0x9, DD = source operand}
unlk
Ax
PST = 0x1, {PST = 0xB, DD = destination operand}
wddata.b
<ea>y
PST = 0x4, {PST = 0x8, DD = source operand
wddata.l
<ea>y
PST = 0x4, {PST = 0xB, DD = source operand
wddata.w
<ea>y
PST = 0x4, {PST = 0x9, DD = source operand
1 _{For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields}
defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi), (d8,PC,Xi).
2 _{For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the operand address}
reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For these line-sized transfers, the
operand data is never captured nor displayed, regardless of the CSR value.
The automatic line-sized burst transfers are provided to maximize performance during these sequential memory access
operations.
3 _{During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state. The}
exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.
Exception ProcessingPST = 0xC,{PST = 0xB,DD = destination},// stack frame
{PST = 0xB,DD = destination},// stack frame
{PST = 0xB,DD = source},// vector read
PST = 0x5,{PST = [0x9AB],DD = target}// handler PC
The PST/DDATA specification for the reset exception is shown below:
Exception ProcessingPST = 0xC,
PST = 0x5,{PST = [0x9AB],DD = target}// handler PC
The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated
as instruction fetches.
For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is
needed for one of the optional marker values or for the taken branch indicator (0x5).
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
5-39