MCF5272CVM66 Datasheet, PDF (310/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Physical Layer Interface Controller (PLIC)
Table 13-1. PLIC Module Memory Map (continued)
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0340
Port2 B2 Data Transmit (P2B2TR)
0x0344
Port3 B2 Data Transmit (P3B2TR)
0x0348
Port0 D Data Transmit
(P0DTR)
Port1 D Data Transmit
(P1DTR)
Port2 D Data Transmit
(P2DTR)
Port3 D Data Transmit
(P3DTR)
0x0350
Port0 GCI/IDL Configuration register (P0CR)
Port1 GCI/IDL Configuration register (P1CR)
0x0354
Port2 GCI/IDL Configuration register (P2CR)
Port3 GCI/IDL Configuration register (P3CR)
0x0358
Port0 Interrupt Configuration register (P0ICR)
Port1 Interrupt Configuration register (P1ICR)
0x035C
Port2 Interrupt Configuration register (P2ICR)
Port3 Interrupt Configuration register (P3ICR)
0x0360
Port0 GCI monitor Rx (P0GMR)
Port1 GCI monitor Rx (P1GMR)
0x0364
Port2 GCI monitor Rx (P2GMR)
Port3 GCI monitor Rx (P3GMR)
0x0368
Port0 GCI monitor Tx (P0GMT)
Port1 GCI monitor Tx (P1GMT)
0x036C
Port2 GCI monitor Tx (P2GMT)
Port3 GCI monitor Tx (P3GMT)
0x0370
Reserved
GCI monitor Tx status
(PGMTS)
GCI monitor Tx abort
(PGMTA)
Reserved
0x0374 Port0 GCI C/I Rx (P0GCIR) Port1 GCI C/I Rx (P1GCIR) Port2 GCI C/I Rx (P2GCIR) Port3 GCI C/I Rx (P3GCIR)
0x0378 Port0 GCI C/I Tx (P0GCIT) Port1 GCI C/I Tx (P1GCIT) Port2 GCI C/I Tx (P2GCIT) Port3 GCI C/I Tx (P3GCIT)
0x037C
Reserved
GCI C/I Tx Status
(PGCITSR)
0x0383
Reserved
GCI C/I D-Channel Status
(PDCSR)
0x0384
Port0 periodic status (P0PSR)
Port1 periodic status (P1PSR)
0x0388
Port2 periodic status (P2PSR)
Port3 periodic status (P3PSR)
0x038C
Aperiodic Interrupt status register (PASR)
Reserved
Loop back Control (PLCR)
0x0390
Reserved
D-Channel Request (PDRQR)
0x0394
Port0 Sync Delay (P0SDR)
Port1 Sync Delay (P1SDR)
0x0398
Port2 Sync Delay (P2SDR)
Port3 Sync Delay (P3SDR)
0x039C
Reserved
Clock Select (PCSR)
13-14
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor