MCF5272CVM66 Datasheet, PDF (212/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

SDRAM Controller
Figure 9-15 shows the timing for exiting SDRAM self-refresh mode. Note that SDCR[GSL] is sampled
on the rising edge of the internal clock. If it is 0, as it is here, SDRAM controller signals become active on
the following negative clock edge.
Internal Clock
T0
SDCLK
SDCR[GSL]
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
SDCR[SLEEP]
SDCLKE
SDADR[13:0]
A10_PRECHG
SDBA[1:0]
SDCS
RAS0
CAS0
SDWE
Figure 9-15. Exit SDRAM Self-Refresh Mode
9-22
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor