MCF5272CVM66 Datasheet, PDF (132/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Debug Support
5.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 5-11, configures the operation of the hardware breakpoint logic that corresponds
with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug module. The
TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as a one-
or two-level trigger. TDR[31–16] define the second-level trigger and bits 15–0 define the first-level
trigger.
NOTE
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR (by clearing TDR[29,13])before defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Second-Level Trigger
31 30 29
28
27
26
25
24
23
22
21
Field TRC EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI
Reset
0000_0000_0000_0000
20
19
18
17
16
EAI EAR EAL EPC PCI
First-Level Trigger
15 14 13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field — EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
Reset
0000_0000_0000_0000
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the WDMREG command.
DRc[4–0]
0x07
Figure 5-11. Trigger Definition Register (TDR)
Table 5-14 describes TDR fields.
Table 5-14. TDR Field Descriptions
Bits
31–30
15–14
29/13
Name
Description
TRC
—
EBL
Trigger response control. Determines how the processor responds to a completed trigger condition. The
trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Reserved, should be cleared.
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint trigger.
Clearing it disables all breakpoints at that level.
5-14
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor