MCF5272CVM66 Datasheet, PDF (93/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

2.7.5 Branch Instruction Execution Times
Table 2-16 shows general branch instruction timing.
Table 2-16. General Branch Instruction Execution Times
Opcode <ea>
Rn
bra
—
bsr
—
jmp
<ea>
—
jsr
<ea>
—
rte
—
rts
—
(An)
—
—
3(0/0)
3(0/1)
—
—
(An)+
—
—
—
—
10(2/0)
5(1/0)
Effective Address
–(An)
—
—
—
—
—
—
(d16,An)
2(0/1)
3(0/1)
3(0/0)
3(0/1)
—
—
(d8,An,Xi*SF)
—
—
4(0/0)
4(0/1)
—
—
ColdFire Core
(xxx).wl
—
—
3(0/0)
3(0/1)
—
—
#<xxx>
—
—
—
—
—
—
Table 2-17 shows timing for Bcc instructions.
Table 2-17. Bcc Instruction Execution Times
Opcode
bcc
Forward Taken
3(0/0)
Forward Not Taken
1(0/0)
Backward Taken
2(0/0)
Backward Not Taken
3(0/0)
2.8 Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. Differences from previous
M68000 family processors include the following:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single, self-aligning system stack pointer
ColdFire processors use an instruction restart exception model but require more software support to
recover from certain access errors. See Table 2-18 for details.
Exception processing can be defined as the time from the detection of the fault condition until the fetch of
the first handler instruction has been initiated. It is comprised of the following four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting SR[S]
and disabling trace mode by clearing SR[T]. The occurrence of an interrupt exception also forces
SR[M] to be cleared and the interrupt priority mask to be set to the level of the current interrupt
request.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on the exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a
peripheral device. The IACK cycle is mapped to a special acknowledge address space with the
interrupt level encoded in the address.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
2-25