MCF5272CVM66 Datasheet, PDF (482/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

IEEE 1149.1 Test Access Port (JTAG)
Figure 21-8 shows the structure of the bypass register.
Figure 21-8. Bypass Register
21.6 Restrictions
The control afforded by the output enable signals using the boundary scan register and the EXTEST
instruction requires a compatible circuit board test environment to avoid configurations that could damage
the device. The user must avoid situations in which the MCF5272 output drivers are enabled into actively
driven networks. Overdriving the TDO driver when it is active is not recommended.
21.7 Non-IEEE 1149.1 Operation
In non-IEEE 1149.1 operation, IEEE 1149.1 test logic must be made transparent to system logic by forcing
the TAP controller into test-logic-reset state, which takes at least five consecutive TCK rising edges with
TMS high. TMS has an internal pull-up resistor and may be left unconnected.
If TMS is unconnected or connected to V_CC, the TAP controller cannot exit test-logic-reset state,
regardless of the TCK state. This requires the TMS, TCK, and TDI inputs to be high.
21-8
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor