MCF5272CVM66 Datasheet, PDF (313/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Physical Layer Interface Controller (PLIC)
13.5.4 B1 Data Transmit Registers (P0B1TR–P3B1TR)
All bits in these registers are read/write and are set on hardware or software reset.
The PnB1TR registers contain four frames of transmit data for channel B1. (P0B1TR is the B1 channel
transmit data for port 0, P1B1TR is B1 transmit for port 1, and so on.) The data are packed from LSB to
MSB.
These registers are aligned on long-word boundaries from MBAR + 0x328 for P0B1TR to
MBAR + 0x334 for P3B1TR. See Section 13.2.3, “GCI/IDL B- and D-Channel Bit Alignment,” for the
frame and bit alignment within the 32-bit word.
31
24
23
16
Field
Frame 0
Frame 1
Reset
1111_1111
1111_1111
R/W
Read/Write
15
8
7
0
Field
Frame 2
Frame 3
Reset
1111_1111
1111_1111
R/W
Read/Write
Addr
MBAR + 0x328 (P0B1TR); 0x32C (P1B1TR); 0x330 (P2B1TR); 0x334 (P3B1TR)
Figure 13-16. B1 Transmit Data Registers P0B1TR–P3B1TR
13.5.5 B2 Data Transmit Registers (P0B2TR–P3B2TR)
All bits in these registers are read/write and are set on hardware or software reset.
The PnB2TR registers contain four frames of transmit data for port n of channel B2. (P0B2TR is the B2
channel transmit data for port 0, P1B2TR is B2 transmit for port 1, and so on.) The data are packed from
LSB to MSB.
These registers are aligned on long-word boundaries from MBAR + 0x338 for P0B2TR to
MBAR + 0x344 for P3B2TR. Please refer to Section 13.2.3, “GCI/IDL B- and D-Channel Bit Alignment”
for the frame and bit alignment within the 32-bit word.
31
24
23
16
Field
Frame0
Frame1
Reset
1111_1111
1111_1111
R/W
Read/Write
15
8
7
0
Field
Frame2
Frame3
Reset
1111_1111
1111_1111
R/W
Read/Write
Addr
MBAR + 0x338 (P0B2TR); 0x33C (P1B2TR); 0x340 (P2B2TR); 0x344 (P3B2TR)
Figure 13-17. B2 Transmit Data Registers P0B2TR–P3B2TR
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-17