MCF5272CVM66 Datasheet, PDF (317/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Bits
15
14–12
11
10
9
8
7–6
5
4
3
2
1
0
Physical Layer Interface Controller (PLIC)
Name
IE
—
GCR
GCT
GMR
GMT
—
DTIE
B2TIE
B1TIE
DRIE
B2RIE
B1RIE
Table 13-4. P0ICR–P3ICR Field Descriptions
Description
Interrupt enable. Allows the port to generate interrupts to the CPU. When cleared, the IE bit masks all
periodic and aperiodic interrupts associated with the respective port.
Reserved, should be cleared.
Interrupt enable for the C/I channel receive.
0 Interrupt masked
1 Interrupt enabled. When set, an interrupt is enabled which occurs when the corresponding GCR
status bit is set.
C/I channel transmit Interrupt enable.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel receive.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel transmit.
0 Interrupt masked
1 Interrupt enabled.
Reserved, should be cleared.
D transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[DTDE] or PnPSR[DTUE] is set.
B2 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2TDE] or PnPSR[B2TUE] is
set.
B1 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B1TDE] or PnPSR[B1TUE] is
set.
D receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[DRDF] or PnPSR[DROE] is
set.
B2 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2RDF] or PnPSR[B2ROE] is
set.
B1 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[B1RDF] or PnPSR[B1ROE] is
set.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-21