MCF5272CVM66 Datasheet, PDF (490/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Electrical Characteristics
23.3.2 Processor Bus Input Timing Specifications
Table 23-7 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the SDCLK output.
All other timing relationships can be derived from these values.
Table 23-7. Processor Bus Input Timing Specifications
Name
Characteristic¹
0–66 MHz
Unit
Min Max
B1a ²
B1b ²
B1c ²
B1d ²
B1e ²
RSTI valid to SDCLK (setup)
TA valid to SDCLK (setup)
TEA valid to SDCLK (setup)
INTx valid to SDCLK (setup)
BKPT valid to PSTCLK (setup)
Control Inputs
6.5 — nS
8 — nS
8 — nS
8 — nS
10 — nS
B1f
Mode selects (BUSW[1:0], WSEL, HiZ) valid to SDCLK (setup) (when RSTI asserted)
8 — nS
B2d SDCLK to asynchronous control inputs (RSTI, TA, TEA, INTx) invalid (hold)
2 — nS
B2e SDCLK to mode selects (BUSW[1,0], WSEL, HIZ) invalid (hold) (when RSTI asserted)
2 — nS
B2f
PSTCLK to asynchronous control input BKPT invalid (hold)
0 — nS
B3
RSTI width low
10T — nS
Data Inputs
B4
Data input (D[31:0]) valid to SDCLK (setup)
14 — nS
B5
SDCLK to data input (D[31:0]) invalid (hold)
0 — nS
1 _{All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.}
2 _{RSTI, TA, TEA, and INTx are synchronized internally. The setup time must be met only if recognition is needed on a particular}
clock edge.
23-6
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor