MCF5272CVM66 Datasheet, PDF (166/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

System Integration Module (SIM)
Table 6-3. SCR Field Descriptions (continued)
Bits
Field
Description
3 BusLock Locks the ownership of the bus.
0 Ownership of the bus is determined by arbitration.
1 Current bus master retains ownership of the bus indefinitely.
2–0
HWR Hardware watchdog reference. Determines how many clocks to wait before timing out a bus cycle when
SPR[HWTEN] is set. The value programmed should be longer than the response time of the slowest
external peripheral in the system.
000 128
001 256
010 512
011 1024
100 2048
101 4096
110 8192
111 16384
6.2.4 System Protection Register (SPR)
The system protection register (SPR), Figure 6-4, provides information about bus cycles that have
generated error conditions. These error conditions can optionally generate an access error exception by
using the enable bits.
Field
Reset
R/W
15
ADC
14
WPV
13
SMV
7
Field ADCEN
Reset
R/W
Address
6
WPVEN
5
SMVEN
12
11
PE
HWT
0000_0000
R/W
10
RPV
9
EXT
8
SUV
4
3
PEEN HWTEN
0000_1011
R/W
MBAR + 0x006
2
RPVEN
1
EXTEN
0
SUVEN
Figure 6-4. System Protection Register (SPR)
Table 6-4 describes SPR fields.
Table 6-4. SPR Field Descriptions
Bits Fields
Description
15, 7
14, 6
13, 5
12, 4
ADC, Address decode conflict. This bit is set when an address matches against two chip selects. If ADCEN is
ADCEN also set, the bus cycle is terminated with an access error exception.
WPV, Write protect violation. This bit is set when a write access is attempted to an area for which the chip select
WPVEN is set to read only. If WPVEN is also set, the bus cycle is terminated with an access error exception.
SMV, Stopped module violation. This bit is set when an access is attempted to an on-chip peripheral whose
SMVEN clock has been stopped. If SMVEN is also set, the bus cycle is terminated with an access error exception.
PE, PEEN Peripheral error. This bit is set when an access to an on-chip peripheral is terminated with a transfer error.
If PEEN is also set, the bus cycle is terminated with an access error exception.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
6-6
Freescale Semiconductor