MCF5272CVM66 Datasheet, PDF (451/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Bus Operation
TA must always be negated before it can be recognized as asserted again. If held asserted into the following
bus cycle, it has no effect and does not terminate the bus cycle.
NOTE
For the MCF5272 to accept the transfer as successful with a transfer
acknowledge, TEA must be negated throughout the transfer.
TA is not used for termination during SDRAM accesses.
20.2.5 Transfer Error Acknowledge (TEA)
An external slave asserts this active-low input signal to abort a transfer. The assertion of TEA immediately
aborts the bus cycle. The assertion of TEA has precedence over the assertion of TA.
The MCF5272 edge-detects and retimes the TEA input. TEA is an asynchronous input signal.
The TEA signal function is available after reset. If TEA is not used, a pullup resistor or gating logic must
be used to ensure the input is inactive. TEA should be negated on the negating edge of the active chip
select. TEA must always be negated before it can be recognized as asserted again. If held asserted into the
following bus cycle, it has no effect and does not abort the bus cycle.
TEA has no affect during SDRAM accesses.
20.3 Bus Exception: Double Bus Fault
When a bus error or an address error occurs during the exception processing sequence for a previous bus
error, a previous address error, or a reset exception, the bus or address error causes a double bus fault. If
the MCF5272 experiences a double bus fault, it enters the halted state. To exit the halt state, reset the
MCF5272.
20.4 Bus Characteristics
The MCF5272 uses the address bus (A[22:0]) to specify the location for a data transfer and the data bus
(D[31:0] or D[31:16]) to transfer the data. Control signals indicate the direction of the transfer. The
selected device or the number of wait states programmed in the chip select base registers (CSBRs), the
chip select option registers (CSORs), the SDRAM configuration and SDRAM timing registers (SDCR,
SDTR) control the length of the cycle.
The MCF5272 clock is distributed internally to provide logic timing. All SRAM and ROM mode bus
signals should be considered as asynchronous with respect to CLKIN. SDCR[INV] allows the SDRAM
control signals to be asserted and negated synchronous with the rising or falling edge of SDCLK. The
SDRAM control signals are BS[3:0], SDBA[1:0], RAS0, CAS0, SDWE, A10_PRECHG, SDCLKE, and
CS7/SDCS.
The asynchronous INT[6:1] signals are internally synchronized to resolve the input to a valid level before
being used.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
20-3