MCF5272CVM66 Datasheet, PDF (54/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

Table xi. UART1 Module Memory Map (continued)
MBAR
Offset
Register Name
0x016C
0x0174
0x0178
0x017C
UART1 RxFIFO Control/Status Register
UART1 CTS Unlatched Input
UART1 RTS O/P Bit Set Command Register
UART1 RTS O/P Bit Reset Command Register
Old Mnemonic
U2RxFCSR
U2IP
U2OP1
U2OP0
New Mnemonic
U1RxFCSR
U1IP
U1OP1
U1OP0
Table xii. SDRAM Controller Memory Map
MBAR
Offset
Register Name
0x0182
0x0186
SDRAM Configuration Register
SDRAM Timing Register
Old Mnemonic
SDCCR
SDCTR
New Mnemonic
SDCR
SDTR
Table xiii. Timer Module Memory Map
MBAR
Offset
Register Name
0x0200
0x0204
0x0208
0x020C
0x0210
0x0220
0x0224
0x0228
0x022C
0x0230
0x0240
0x0244
0x0248
0x024C
0x0250
0x0260
0x0264
0x0268
Timer 0 Mode Register
Timer 0 Reference Register
Timer 0 Capture Register
Timer 0 Counter Register
Timer 0 Event Register
Timer 1 Mode Register
Timer 1 Reference Register
Timer 1 Capture Register
Timer 1 Counter Register
Timer 1 Event Register
Timer 2 Mode Register
Timer 2 Reference Register
Timer 2 Capture Register
Timer 2 Counter Register
Timer 2 Event Register
Timer 3 Mode Register
Timer 3 Reference Register
Timer 3 Capture Register
Old Mnemonic
TMR1
TRR1
TCR1
TCN1
TER1
TMR2
TRR2
TCR2
TCN2
TER2
TMR3
TRR3
TCR3
TCN3
TER3
TMR4
TRR4
TCR4
New Mnemonic
TMR0
TRR0
TCAP0
TCN0
TER0
TMR1
TRR1
TCAP1
TCN1
TER1
TMR2
TRR2
TCAP2
TCN2
TER2
TMR3
TRR3
TCAP3
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
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Freescale Semiconductor