MCF5272CVM66 Datasheet, PDF (214/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

DMA Controller
10.2 DMA Address Modes
The DMA address mode determines how the address output by the channel is updated after a transfer to
be ready for the next transfer. The two following modes are supported:
• Static address mode—The address remains unchanged after the transfer completes. This mode
should be used when the source or destination address is the FIFO data port of an on-chip
peripheral.
• Increment address mode—In increment address mode, the address is incremented at the end of the
transfer by the number of bytes transferred. This mode should be used when a source or destination
address is in external memory.
10.3 DMA Controller Registers
The MCF5272 DMA controller supports a single DMA channel which can be used for
memory-to-memory transfers.
10.3.1 DMA Mode Register (DMR)
The DMR controls various operation modes, principally the request and addressing modes. Fields include
the transfer size and modifier, transfer direction, channel enable and reset.
31
30
29
Field RESET EN
Reset
R/W
—
0000_0000_0000_0000
R/W
20
19
18
17 16
RQM
—
15
Field —
Reset 0
R/W
Addr
14
13
DSTM
12
10
DSTT
9
8
DSTS
7
6
5
4
2
— — SRCM
SRCT
01
1_00
01
00
1
1_01
R/W
MBAR + 0x00E0
Figure 10-1. DMA Mode Register (DMR)
1
0
SRCS
01
Table 10-2 describes DMR fields.
Table 10-2. DMR Field Descriptions
Bits Name
Description
31
30
29–20
RESET Reset. Writing a 1 to this location causes the DMA controller to reset to a condition where no transfers are
taking place. EN is cleared, preventing new transfers.
EN Enable. Controls whether the DMA channel is enabled to perform transfers.
0 DMA transfers are disabled.
1 DMA transfers are enabled. The DMA controller can respond to requests from the peripheral or generates
internal requests in dual address mode, so long as the conditions described under the DMA interrupt
flags (see Section 10.3.2, “DMA Interrupt Register (DIR)”) do not prevent transfers from going ahead.
— Reserved, should be cleared.
10-2
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor