MCF5272CVM66 Datasheet, PDF (82/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

ColdFire Core
Table 2-6. Notational Conventions (continued)
Instruction
Operand Syntax
<ea>y,<ea>x
<label>
<list>
<shift>
<size>
bc
# <vector>
<>
<xxx>
dn
SF
Source and destination effective addresses, respectively
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
Shift operation: shift left (<<), shift right (>>)
Operand data size: byte (B), word (W), longword (L)
Instruction cache
Identifies the 4-bit vector number for trap instructions
identifies an indirect data address referencing memory
identifies an absolute address referencing memory
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+
Arithmetic addition or postincrement indicator
–
Arithmetic subtraction or predecrement indicator
x
Arithmetic multiplication
/
Arithmetic division
~
Invert; operand is logically complemented
&
Logical AND
|
Logical OR
^
Logical exclusive OR
<<
Shift left (example: D0 << 3 is shift D0 left 3 bits)
>>
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→
Source operand is moved to destination operand
←→
Two operands are exchanged
sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition> Test the condition. If the condition is true, the operations in the then clause are performed. If the condition
then <operations> is false and the optional else clause is present, the operations in the else clause are performed. If the
else <operations> condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc
instruction description as an example.
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MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor