MCF5272CVM66 Datasheet, PDF (77/544 Pages) Freescale Semiconductor, Inc – MCF5272 ColdFire® Integrated Microprocessor

ColdFire Core
2.2.2.3 Cache Control Register (CACR)
The CACR controls operation of the instruction and data cache memory. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. See Section 4.5.3.1, “Cache Control Register (CACR).”
2.2.2.4 Access Control Registers (ACR0–ACR1)
The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions.
Attributes include definition of cache mode, write protect, and buffer write enables. See Section 4.5.3.2,
“Access Control Registers (ACR0 and ACR1).”
2.2.2.5 ROM Base Address Register (ROMBAR)
The ROMBAR base address register determines the base address of the internal ROM module and
indicates the types of references mapped to it. The ROMBAR includes a base address, write-protect bit,
address space mask bits, and an enable. Note that the MCF5272 ROM contains data for the HDLC module
and is not user programmable. See Section 4.4.2.1, “ROM Base Address Register (ROMBAR).”
2.2.2.6 RAM Base Address Register (RAMBAR)
The RAMBAR register determines the base address location of the internal SRAM module and indicates
the types of references mapped to it. The RAMBAR includes a base address, write-protect bit, address
space mask bits, and an enable. The RAM base address must be aligned on a 0-modulo-4-Kbyte boundary.
See Section 4.3.2.1, “SRAM Base Address Register (RAMBAR).”
2.2.2.7 Module Base Address Register (MBAR)
The module base address register (MBAR) defines the logical base address for the memory-mapped space
containing the control registers for the on-chip peripherals. See Section 6.2.2, “Module Base Address
Register (MBAR).”
2.3 Integer Data Formats
Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or
instructions. The operand size for each instruction is either explicitly encoded in the instruction or
implicitly defined by the instruction operation.
Table 2-4. Integer Data Formats
Operand Data Format
Bit
Byte integer
Word integer
Longword integer
Size
1 bit
8 bits
16 bits
32 bits
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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