900844 Datasheet, PDF (95/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
ADC SUBSYSTEM
Touch Screen Pen detection bias can be enabled via the PENDETEN bit in the ADCCNTL1 register. When this bit is enabled
and a pen touch is detected, the PENDET bit in register ADCINT is set and the PMICINT pin is asserted. This is to interrupt the
system, because a touch screen pen touch has been detected at the next ADC cycle, unless the interrupt is masked.
The prior reference for the touch screen (Touch Bias) is TSREF and is powered from VCORE. In touch screen operation,
TSREF is a dedicated regulator. No loads other than the touch screen should be connected here. When the ADC performs non
touch screen conversions, the ADC does not rely on TSREF and the reference can be disabled.
The readouts are designed such that the on chip switch resistances are of no influence to the overall readout. The readout
scheme does not account for contact resistances, as present in the touch screen connectors. Therefore, the touch screen
readings have to be calibrated by the user or in the factory, where one has to point with a stylus to the opposite corners of the
screen. When reading out the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate with '0' for a coordinate equal
to X- and full scale '1023' when equal to X+. When reading out the Y-coordinate, the 10-bit ADC reading represents a 10-bit
coordinate with '0' for a coordinate equal to Y- and full scale '1023' when equal to Y+. When reading the contact resistance the
10-bit ADC reading represents the voltage drop over the contact resistance created by the known current source multiplied by 2.
Table 66. Touch Screen System Requirements
Description
Plate Resistance X, Y
Resistance Between Plates, Contact
Capacitance Between Plates
Contact Resistance Current Source
Interrupt Current Source
Interrupt Threshold
Current Source Inaccuracy
Quiescent Current (Active Mode)
Max Load Current (Active Mode)
Settling Time (Position Measurement)
Symbol
Min
Typ
Max
Unit
-
100
-
1000
Ω
-
180
-
1200
Ω
-
0.5
2.0
-
nF
-
-
100
-
μA
-
-
20
-
μA
-
40
-
60
kΩ
-
-
-
20
%
-
20
-
μA
-
-
20
mA
-
3.0
-
5.5
μs
ADC STATUS/CONTROL REGISTERS AND BIT DESCRIPTION
Reference the Table 67 for read/write conditions and default state for each of these registers
Table 67. ADC Interrupt/Mask Registers Structure and Bits Description
Name
Bits
Description
RND
PENDET
ADCINT (ADDR 0x5F - R - Default Value: 0x00)
0 ADC Round Robin Cycle Completion Interrupt
x0 = Not Completed
x1 = Completed
1 ^{Touch Screen Pen Detection Interrupt}
x0 = Pen Not Detected
x1 = Pen Detected
Reserved
MRND
7:2 ^Reserved
MADCINT (ADDR 0x60 - R/W -Default Value: 0x00)
0 ^{ADC Round Robin Cycle Completion Interrupt Mask}
x0 = Unmask
x1 = Mask
MPENDET
Reserved
1 ^{Touch Screen Pen Detection Interrupt Mask}
x0 = Unmask
x1 = Mask
7:2 Reserved
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
95