900844 Datasheet, PDF (100/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
GPIOS
GPIO STATUS/CONTROL REGISTERS AND BIT DESCRIPTION
GPIO module has a single 8-bit status and control register assigned to it. See Table 72 for details.
The “x” in the bit names in the tables is from 0 to 7 for the GPIOs.
Table 72. GPIO Register Structure and Bits Description
Name Bits
Description
DRVx
0 ^{GPIOx Output Driver Type}
x0 = Open Drain
x1 = CMOS
GPIOCNTLx (x = 0 to 7)
DIRx
1 GPIOx Direction Configuration
x0 = Output (Type selected by Bit 0)
x1 = Input (Bit 0 is ignored)
DATAINx 2 ^{The value in the DATA_IN bit reflects the electrical state of the GPIOx pin at the time the register read was initiated. When}
Bit 1, DIRECTION, is 0 (Output Mode), the contents of this register are not required to be updated on reads and is assumed
to be invalid by the system controller. The PMIC should de-bounce the inputs over 1-10 ms to insure a clean transition.
X0 = Electrical Low ⁽¹⁹⁾
x1 = Electrical High ⁽¹⁹⁾
DATAOUTx 3
The value in the DATA_OUT bit reflects the desired electrical output state of the GPIOx pin. When Bit 1, DIRECTION, is 1
(Input Mode), the contents of this register may still be read or written, but will not be reflected until the GPIOx is reverted
to an output (Bit 1, DIRECTION, is 0)
x0 = Electrical Low ⁽¹⁹⁾
x1 = Electrical High (CMOS) or High-impedance Output (Open-Drain) ⁽¹⁹⁾
INTCTLx
5:4 ^{These bits set the interrupt definition. The MASK (00) determines if the corresponding interrupt flag bit is set or not on an}
interrupt. The other logic levels will set the corresponding interrupt flag bit in the register upon the specific edge detection
defined by the level. They will also set bit 4 of the 1st level INTERRUPT register, see section Interrupt Controller for more
details. ⁽²⁰⁾
x0 = Mask.
x1 = Negative Edge
x2 = Positive Edge
x3 = Both Edges
GPIDBNCx 7:6
These bits set the debounce time on the GPIOx when configured as inputs
x0 = No Debounce
x1 = 10 ms
x2 = 20 ms
x3 = 30 ms
GPIINT0
GPIOINT (ADDR 0xE8 - R - Default Value: 0x00)
0 GPIO0 Interrupt Flag
x0 = No Interrupt occurred or Masked Interrupt
x1 = Interrupt occurred
GPIINT1
1 ^{GPIO1 Interrupt Flag}
x0 = No Interrupt occurred or Masked Interrupt
x1 = Interrupt occurred
GPIINT2
2 ^{GPIO2 Interrupt Flag}
x0 = No Interrupt occurred or Masked Interrupt
x1 = Interrupt occurred
GPIINT3
3 GPIO3 Interrupt Flag
x0 = No Interrupt occurred or Masked Interrupt
x1 = Interrupt occurred
Notes
19. See GPIOs electrical characteristics on Table 3
20. An unintended interrupt is caused if interrupt settings are reconfigured in the middle of an application, e.g. re-setting interrupt detection
from detecting an interrupt on both edges to an interrupt on the rising edge. In this case, to mask any unwanted interrupt, change the
GPIO interrupt detection to the new configuration, then clear Level 1 and level 2 interrupts, finally unmask the GPIO Interrupt.
900844
100
Analog Integrated Circuit Device Data
Freescale Semiconductor