900844 Datasheet, PDF (31/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
Figure 6. SPI Read from PMIC Diagram (One Address/Data Packet shown)
Figure 7. SPI Write to PMIC Diagram (One address/Data Packet Shown)
Figure 8. SPI Interface Timing Diagram (Processor Input capacitance is 3.0 pF)
INTERRUPT CONTROLLER
Control
The PMIC informs the system of important events using interrupts. Unmasked interrupt events are signaled to the host by
driving the PMICINT pin high.
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. If a
new interrupt occurs while the controller clears an existing interrupt bit, the interrupt line will remain high.
Each interrupt can be masked by setting the corresponding mask bit to a ‘1’. As a result, when a masked interrupt bit goes
high, the interrupt line will not go high. A masked interrupt can still be read from the register. If a masked interrupt bit was already
high, the interrupt line will go high after unmasking.
The following is the interrupt handling mechanism which has inherent latency that the clients must expect:
1. PMIC interrupts SCU, if both the 1st and 2nd level bits
are not masked.
3. SCU then traverses all the branches of the interrupt
tree where events are indicated.
2. SCU reads PMIC master, 1st level, interrupt event
register.
4. SCU will service events in leaf node registers.
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
31