900844 Datasheet, PDF (30/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
OVERVIEW
This section addresses the various interfaces and I/Os between the PMIC solution and the rest of the system.
The system control interface includes the following:
• SPI interface.
• Interrupt controller
• Platform sideband signals
• Special registers
SPI INTERFACE
The 900844 contains a SPI interface port which allows a host controller to access the register set. Using these registers,
900844 resources can be controlled. The registers also provide information on the PMIC status, as well as information on external
signals.
The addressable register map spans 1024 registers of 8 data bits each. The map is not fully populated. A detailed structure
of the register set along with bit names, positions, and basic descriptions, are given in Table 74. Expanded bit descriptions are
included in the individual functional sections for application guidance.
Note that not all bits are truly writable. Refer to the individual sub-circuit descriptions and Table 74 to determine the read/write
capability of each bit.
Table 5. SPI Interface Pin Functionality
Pin Name
SPI Functionality
SPICLK
SPI Clock Input (up to 25 MHz)
MOSI
Master Out / Slave In (Serial Data In)
MISO
Master In / Slave Out (Serial Data Out)
SPICSB
Chip Select (Active Low)
SPIVCC
SPI Bus Supply - 1.8 V typical
The System Controller Unit (SCU) within the Platform Controller Hub (PCH) is the master, while the PMIC is the slave. The
SPI interface operates at a typical frequency of 12.5 MHz, and at a maximum frequency of 25 MHz, with lower speeds supported.
The SPI interface is configured in mode 1: clock polarity is active high (CPOL = 0), and data is latched on the falling edge of
the clock (CPHA = 1). The chip select signal, SPICSB, is active low. The SPICSB line must remain active during the entire SPI
transfer. The MISO line will be tri-stated while SPICSB is high.
The SPI frame consists of 24 bits: a Read/Write bit, a 10-bit address code (MSB first), 5 "dead" bits and 8 data bits (also MSB
first). The Read/Write bit selects whether the SPI transaction is a read or a write: for a write operation, the R/W bit must be a one;
for a read operation, it must be a zero.
For a read transaction, any data on the MOSI pin after the address bits is ignored. The MISO pin will output the data field
pointed to by the 10-bit address loaded at the beginning of the SPI sequence. SPI read backs of the address field and unused
bits are returned as zero. For read operations, the PMIC supports address auto-increment.
For a write operation, once all the data bits are written, the data is transferred into the registers on the falling edge of the 24th
clock cycle. All unused SPI bits in each register must be written to a zero.
To start a new SPI transfer, the SPICSB line must go inactive and then active. After the LSB of data is sent, if the SPICSB line
is held low, up to seven additional address/data packets may be sent as writes to the PMIC. Refer to the VRCOMP Pin section.
The following diagrams illustrate the SPI Write Protocol, SPI Read Protocol, and SPI Timing.
900844
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Analog Integrated Circuit Device Data
Freescale Semiconductor