900844 Datasheet, PDF (40/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
SCU
SCU
SCU
SCU
SCU
Figure 16. Relationship Between the VID/VIDEN Pins, the DPV1VRD Bit, and VRCOMP Signal
SPECIAL REGISTERS
Vendor ID and Version ID
The Vendor ID and other version details can be read via the Identification bits. These are hard-wired on the chip.
Table 12. Vendor ID Registers Structure and Bits Description
Name
Bits
Description
VENDID1
REV1
Reserved
ID1 (ADDR 0x00 - R - Default Value: 0x28)
2:0
Chip1 Vendor ID
5:3
Chip1 Revision ID
7:6
Reserved
VENDID2
REV2
Reserved
Reserved
ID2 (ADDR 0x01 - R - Default Value: 0x00)
2:0
Chip2 Vendor ID
5:3
Chip2 Revision ID
7:6
Reserved
ID3 (ADDR 0x02 - R - Default Value: 0x00)
7:0
Reserved
Reserved
ID4 (ADDR 0x03 - R - Default Value: 0x00)
7:0
Reserved
Embedded Memory
There are 24 memory registers of general purpose embedded memory, which are accessible by the processor to store critical
data during power down. These registers consist of 8 in the general purpose registers area, and 16 more in the Freescale
dedicated register area. General memory registers are called MEMx [MEM1, MEM2… MEM8]. The Freescale dedicated registers
are called FSLMEMx [FSLMEM1, FSLMEM2… FSLMEM16]. The data written to these registers is maintained by the coin cell,
when the main battery is deeply discharged or removed, and is part of the RTC block. The content of the embedded memory is
reset by RTCPORB. The banks can be used for any system need, for bit retention with coin cell backup.
900844
40
Analog Integrated Circuit Device Data
Freescale Semiconductor