900844 Datasheet, PDF(32/118 Page) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

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900844 Datasheet, PDF (32/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

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FUNCTIONAL DEVICE OPERATION

SYSTEM CONTROL INTERFACE

When an unmasked interrupt event happens:

â¢ The 2nd level bit is set.

â¢ The 1st level bit is set by a rising edge sent from the 2nd level register, and the PMICINT signal goes from low to high

â¢ When the system controller, the SCU, reads the 1st level register the 2nd level registers that were set, remain set. Any unset

registers are free to accept an interrupt event.

â¢ When the 1st level register is read, any 1st level register bits that were set at the point the SPI read strobe shifts the register

value into the SPI transmit shift register, that bit will be cleared by the SPI self clear signal immediately following the read

strobe. This allows new interrupts to be recorded without being lost. If all unmasked 1st level bits get cleared by the read, the

PIMCINT pin will de-assert. If a new unmasked 1st level interrupt event happens, just after the read of the 1st level register,

the PIMCINT pin interrupt pin will remain asserted. The SCU reads each 2nd level register and these are cleared on read.

â¢ When the 2nd level register is read, any 2nd level register bits that were set at the point the SPI read strobe sweeps, the

register value into the SPI transmit shift register, that bit will be cleared by the SPI self clear signal immediately following the

read strobe. This allows new interrupts to be recorded without being lost. If a new unmasked 2nd level interrupt event happens

just after the read of the 2nd level register, the PMICINT pin will assert if the 1st level bit is not masked.

Table 6. Interrupt Registers Summary

Block

ADDR

Name

D0 Initial

IRQ

0x04 INTERRUPT R

EXT

AUX VRFAULT GPIO

RTC

CHR

ADC

PWRBTN 0x00

IRQ

0x05 INTMASK R/W MEXT MAUX MVRFAUL MGPIO MRTC

MCHR

MADC MPWRBTN 0xFA

RTC

0x1C

RTCC

IRQF PF (=0)

RSVD

0x00

POWER

0x30 VRFAULTIN R

RSVD RSVD

RSVD

VRFAIL

BATOCP

THRM

0x00

POWER

0x31 MVRFAULTI R/W RSVD

RSVD

RSVD MVRFAIL MBATOCP MTHRM 0x03

ADC

0x5F ADCINT

RSVD RSVD

RSVD

RSVD OVERFLOW PENDET

RND

0x00

ADC

0x60 MADCINT R/W RSVD RSVD

RSVD

RSVD MOVERFLO MPENDET

MRND

0x00

GPIO

0xE8 GPIOINT

R GPIINT7 GPIINT6 GPIINT5 GPIINT4 GPIINT3 GPIINT2

GPIINT1 GPIINT0 0x00

Notes

9. Because of the design of the clear on read logic, any interrupt event is allowed to happen at any time. If the interrupt event happens

close to when a read of the interrupt register happens, if the SPI read captures that interrupt bit as being set, then that bit will get cleared.

If the read does not capture the bit as being set, it will not be cleared. In this way no interrupt events are lost.

10. The 2nd level interrupts that get "Ored" together to set the 1st level interrupt bits can block other 2nd level interrupts from setting the 1st

level interrupt register. This is because if any of the 2nd level interrupts is high, the output of the OR will remain high, blocking the other

2nd level interruptâs rising edge. This should not be a problem. because when the 2nd level register is read, the SCU will see all the bits

that are active when it is read. The software will decide which one to service first, just as it needs to do when more than one 1st level

interrupt bits are set when that register is read.

11. Masking has no affect on interrupt bits being set or cleared. Masking just prevents the interrupt event from asserting the interrupt pin. If

an interrupt bit is set, but is masked, the interrupt pin does not assert. If the mask bit is cleared while the bit is still set, the interrupt pin

will assert. Most interrupt registers have 1st and 2nd level mask bits. Both mask bits must be in the unmasked state to generate an

interrupt to the SCU.

12. Some 2nd level interrupt registers are level sensitive. If the level that sets these interrupts registers is active when the register is read,

it will clear during the active time of the clear on read signal and then reassert. This will reassert the 1st level interrupt bit.

13. The GPIO interrupts do not have interrupt masking bits, they have interrupt prevention bits. This is controlled by bits 5:4 of the GPIO

control register. See GPIOs for more details on using the GPIO as interrupt inputs.

14. Interrupts generated by external events are de-bounced. Therefore, the event needs to be stable throughout the de-bounce period

before an interrupt is generated. Nominal de-bounce periods for each event are documented in Table 7. Due to the asynchronous nature

of the de-bounce timer, the effective de-bounce time can vary slightly.

Interrupt Bit Summary

Table 7 summarizes all 1st and 2nd level interrupt bits associated with the Interrupt Controller. For more detailed behavioral

descriptions, refer to the related sections.

900844

Analog Integrated Circuit Device Data

Freescale Semiconductor

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